The present invention relates to an A/D converter and, more particularly, to an A/D converter performing pipeline processing, which can vary resolution.
With digitization and speedup of signal processing in information communication fields as well as downsizing and weight-reduction of information communication devices, speedup and reduction in power consumption are required of A/D converters which become key devices in digital signal processing. In recent years, a pipeline A/D converter has increasingly been employed as a configuration of an A/D converter to meet the requirements. First of all, the construction and operation of a conventional pipeline A/D converter will be described.
FIG. 17 is a block diagram illustrating a general pipeline A/D converter of 5-bit output, using three pipeline stages of 1.5-bit output, and a final pipeline stage of 2-bit output (refer to Japanese Published Patent Application No. Hei.6-85672, Japanese Published Patent Application No. Hei.10-173528, and xe2x80x9cCMOS DATA CONVERTERS FOR COMMUNICATIONSxe2x80x9d by Mikael Gustavsson, J. Jacob Wikner, Nianxiong Nick Tan, KLUWER ACADEMIC PUBLISHERS (ISBN-0-7923-7780-X)).
The pipeline A/D converter is supplied with an analog input signal 1 as an input, and outputs a digital output signal 2. The analog input signal 1 indicated by a partial analog voltage value P0 is connected to a first pipeline stage 3. An output of the first pipeline stage 3, which is indicated by a partial analog voltage value P1, is connected to a second pipeline stage 4. An output of the second pipeline stage 4, which is indicated by a partial analog voltage value P2, is connected to a third pipeline stage 5. An output of the third pipeline stage 5, which is indicated by a partial analog voltage value P3, is connected to a fourth pipeline stage 6. On the other hand, partial digital values M1L1-M4L4 obtained in the respective pipeline stages are connected to a coding circuit 7. There is a case where the analog input signal 1 is connected to the first pipeline stage 3 via a sampling/hold circuit (not shown). The foregoing is the construction of the pipeline A/D converter.
Next, a description will be given of the operation of the pipeline A/D converter for converting the analog voltage values into the digital values. When the analog input signal 1 indicated by the partial analog voltage value P0 is input to the first pipeline stage 3, the first pipeline stage 3 outputs the partial digital value M1L1 which is a binary code having 1.5 bits of information and constitutes a most significant bit of the digital output signal 2, and the partial analog voltage value P1, according to the analog input signal 1. The partial digital value M1L1 and the partial analog voltage value P1 are input to the coding circuit 7 and the second pipeline stage 4, respectively.
Likewise, when the partial analog voltage value P1 is input to the second pipeline stage 4, the second pipeline stage 4 outputs the partial digital value M2L2 which is a binary code having 1.5 bits of information, and the partial analog voltage value P2, according to the partial analog voltage value P1. The partial digital value M2L2 and the partial analog voltage value P2 are input to the coding circuit 7 and the third pipeline stage 5, respectively. Likewise, when the partial analog voltage value P2 is input to the third pipeline stage 5, the third pipeline stage 5 outputs the partial digital value M3L3 which is a binary code having 1.5 bits of information, and the partial analog voltage value P3, according to the partial analog voltage value P2. The partial digital value M3L3 and the partial analog voltage value P3 are input to the coding circuit 7 and the third pipeline stage 6, respectively. Further, when the partial analog voltage value P3 is input to the fourth pipeline stage 6, the fourth pipeline stage 6 outputs the partial digital value M4L4 which is a binary code having 2 bits of information and constitutes a least significant bit, according to the partial analog voltage value P3. The partial digital value M4L4 is input to the coding circuit 7.
The partial digital value L1 and the partial digital value M2, the partial digital value L2 and the partial digital value M3, and the partial digital value L3 and the partial digital value M4 have overlap portions (0.5 bit), respectively, to increase reliability in the conversion process, and the digital output signal 2 which is a binary code and has 5-bit resolution is consequently outputted by coding these digital values in the coding circuit 7. The foregoing is the operation of the pipeline A/D converter.
Next, a description will be given of the constructions and operations of the general pipeline stages constituting the conventional pipeline A/D converter.
Hereinafter, the constructions of the i-th (first to fourth) pipeline stages will be described.
FIG. 18 is a block diagram illustrating the specific construction of each of the first to third pipeline stages 3-5 shown in FIG. 17. Each of the first to third pipeline stages 3-5 is supplied with, as an input, a first partial analog voltage value 8 indicated by Pixe2x88x921, and outputs a partial digital value 9 indicated by MiLi, and a second partial analog voltage value 10 indicated by Pi. The first partial analog voltage value 8 is connected to a first offset addition unit 11, an output of the first offset addition unit 11 is connected to a partial A/D converter 12, an output of the partial A/D converter 12 is connected to a partial D/A converter 13, an output of the partial D/A converter 13 is connected to a second offset addition unit 14, an output of the second offset addition unit 14 and the first partial analog voltage value 8 are connected to a subtracter 15, an output of the subtracter 15 is connected to an arithmetic amplifier 16, an output of the arithmetic amplifier 16 becomes the second partial analog voltage value 10, and an output of the partial A/D converter 12 becomes the partial digital value 9.
On the other hand, FIG. 19 is a block diagram illustrating the specific construction of the fourth pipeline stage 6 shown in FIG. 17. The fourth pipeline stage 6 is supplied with, as an input, a first partial analog voltage value 8 indicated by Pixe2x88x921, and outputs a partial digital value 9 indicated by MiLi. The first partial analog voltage value 8 is connected to a partial A/D converter 12. An output of the partial A/D converter 12 becomes the partial digital value 9. The foregoing is the constructions of the pipeline stages.
Hereinafter, the operations of the i-th (first to fourth) pipeline stages will be described.
In each of the first to third pipeline stages 3-5, the first offset addition unit 11 adds an offset voltage value equivalent to xe2x88x920.5 LSB, as a first offset voltage value 17, to the Pixe2x88x921 that is the inputted first partial analog voltage value 8, and the A/D converter 12 performs A/D conversion on the Pixe2x88x921, thereby outputting, as the partial digital value 9, [00,01,10] which are binary codes each corresponding to 1.5-bit output and having Mi as a higher-order bit and Li as a lower-order bit. Further, the partial D/A converter 13 performs D/A conversion on the partial digital value 9, and the second offset addition unit 14 adds an offset voltage value equivalent to +0.5 LSB, as a second offset voltage value 18, to a result of the D/A conversion. Then, the output from the second offset voltage value 18 and the first partial analog voltage value 8 are input to the subtracter 15, and a difference voltage value between them is obtained, and the difference voltage value is amplified by the arithmetic amplifier 16, thereby obtaining the Pi as the second partial analog voltage value 10. The foregoing is the operation of each of the first to third pipeline stages 3-5.
FIG. 20 is a diagram illustrating relationships of the first partial analog voltage value Pi1 which is an input to each of the first to third pipeline stages 3-5, to the partial digital value MiLi and the second partial analog voltage value Pi which are outputs from each of the first to third pipeline stages 3-5. Although, in FIG. 20, a GND level is employed as a reference level of the first and second partial analog voltage values, the reference level may be arbitrarily set. Further, FS indicates a full-scale voltage value of the first to third pipeline stages 3-5.
On the other hand, in the fourth pipe line stage 6, the partial A/D converter 12 performs A/D conversion on the Pixe2x88x921 that is the first partial analog voltage value 8, thereby outputting, as the partial digital value 9, [00,01,10,11] which are binary codes each corresponding to 2-bit output and having Mi as a higher-order bit and Li as a lower-order bit. The foregoing is the operation of the fourth pipeline stage 6.
FIG. 21 is a diagram illustrating a relationship between the first partial analog voltage value Pixe2x88x921 that is an input to the fourth pipeline stage 6 and the partial digital value MiLi that is an output from the fourth pipeline stage 6. Although, in FIG. 21, a GND level is employed as a reference level of the first partial analog voltage value, the reference level may be arbitrarily set, as described for the first to third pipeline stages 3-5. Further, FS indicates a full-scale voltage value of the fourth pipeline stage 6. The operations of the pipeline stages are as described above.
Next, the construction and operation of the general coding circuit as a component of the pipeline A/D converter will be described in detail.
FIG. 22 is a block diagram illustrating the construction of the coding circuit 7. The coding circuit 7 receives the partial digital values M1L1-M3L3 which are outputted from the first to third pipeline stages 3-5, each value being constituted by a binary code of 1.5 bits, and the partial digital value M4L4 which is outputted from the fourth pipeline stage 6 and is constituted by a binary code of 2 bits, and the coding circuit 7 outputs the digital output signal 2 (D4-D0).
The partial digital value M1 is connected to an A1 terminal as an input terminal of a half adder 19, and the partial digital value L1 is connected to an A2 terminal as an input terminal of a full adder 20. The partial digital value M2 is connected to a B2 terminal as an input terminal of the full adder 20, and the partial digital value L2 is connected to an A3 terminal as an input terminal of the full adder 21. The partial digital value M3 is connected to a B3 terminal as an input terminal of the full adder 21, and the partial digital value L3 is connected to an A4 terminal as an input terminal of the half adder 22. The partial digital value M4 is connected to a B4 terminal as an input terminal of the half adder 22, and the partial digital value L4 becomes D0 that is a least significant bit of the digital output signal 2.
Further, a result of addition S4 from the half adder 22 becomes D1 that is the second bit of the digital output signal 2. A carry signal Co4 from the half adder 22 is connected to a carry signal input terminal Ci3 of the full adder 21. A result of addition S3 from the full adder 21 becomes D2 that is the third bit of the digital output signal 2. A carry signal Co3 from the full adder 21 is connected to a carry signal input terminal Ci2 of the full adder 20. A result of addition S2 from the full adder 20 becomes D3 that is the fourth bit of the digital output signal 2. A carry signal Co2 from the full adder 20 is connected to an input terminal B1 of the half adder 19. A result of addition S1 from the half adder 19 becomes D4 that is a most significant bit of the digital output signal 2.
The A1 to A4 terminals and the B1 to B4 terminals as the input terminals of the half adders and the full adders are interchangeable, and the above-described connections are not necessarily required. Further, although the coding circuit 7 is constituted by the half adders and the full adders, it may be constituted by other logic circuits. The foregoing is the construction of the coding circuit 7.
Next, the operation of the coding circuit 7 will be described. The coding circuit 7 outputs the partial digital value L4 as the least significant bit D0 of the digital output signal 2. Further, the half adder 22 adds the partial digital value M4 and the partial digital value L3, and a result of addition is outputted as the second bit D1 of the digital output signal 2. At this time, if a carry occurs, a carry signal is sent to the full adder 21. Further, the full adder 21 adds the partial digital value M3, the partial digital value L2, and the carry signal of the half adder 22, and a result of addition is outputted as the third bit D2 of the digital output signal 2. When a carry occurs, a carry signal is sent to the full adder 20. Further, the full adder 20 adds the partial digital value M2, the partial digital value L1, and the carry signal of the full adder 21, and a result of addition is outputted as the fourth bit D3 of the digital output signal 2. When a carry occurs, a carry signal is sent to the half adder 19. Further, the half adder 19 adds the partial digital value M1 and the carry signal of the total adder 20, and a result of addition is outputted as the most significant bit D4 of the digital output signal 2. The foregoing is the operation of the coding circuit.
The conventional A/D converter is constructed as described above. Since a mobile communication device such as a handy phone is driven by a battery or the like, reduction in power consumption is required of an A/D converter which is employed in a circuit for improving communication quality in digital communication, for downsizing and weight-reduction of the mobile communication device and long-hours drive of the battery or the like. On the other hand, when the mobile communication device receives information, the intensity of radio wave to be received varies due to obstructions such as buildings or a change in communication distance from a base station to the mobile communication device, and therefore, resolution required of the A/D converter varies according to variations in the radio wave intensity that depends on the place where the device is used.
In the conventional pipeline A/D converter described above, however, the number of bits in the digital output does not change even when the resolution requested by the mobile communication system changes, and all of the pipeline stages are operated, resulting in an impediment to reduction in power consumption of the A/D converter.
On the other hand, in order to solve the above-mentioned problem, Japanese Published Patent Application No. Hei.6-85672 proposes a pipeline A/D converter which can vary resolution of a digital value to be output, by halting operations of A/D converters for determining lower-order bits, according to a given request signal.
However, as described above, in the construction of the pipeline A/D converter which is commonly used at present, the digital output of each pipeline stage has an overlap portion with the digital output of the pipeline stage constituting the higher-order bit, and therefore, the higher-order bit cannot be determined until the lower-order bit is determined. For example, when [M1L1,M2L2,M3L3] are [01,01,01] as shown in FIG. 26(a), [0111] is outputted as an arithmetic result. However, when [M1L1,M2L2,M3L3] are [01,01,10] as shown in FIG. 26(b), an arithmetic result, which should be [1000] actually, becomes [011] because [M3L3] is unknown by halting the pipeline stage 5. In this way, since the output of the most significant bit might be determined by the output of the least significant bit, if the operation of the A/D converter for determining the lower-order bit is simply halted, the requested resolution cannot be realized and, worse yet, a breakdown might occur in the output from the A/D converter.
The present invention is made to solve the above-described problems and has for its object to provide a pipeline A/D converter which can operate with reduced power consumption, by driving only pipeline stages that are required for realizing requested resolution while halting pipeline stages that are not required for realizing the resolution, when resolution of the A/D converter requested by the system is changed, and further, an A/D converter which can prevent a breakdown in an output from the A/D converter, which breakdown might occur when the operations of the unnecessary pipeline stages are halted.
Other objects and advantages of the invention will become apparent from the detailed description that follows. The detailed description and specific embodiments described are provided only for illustration since various additions and modifications within the scope of the invention will be apparent to those of skill in the art from the detailed description.
According to a first aspect of the present invention, an A/D converter comprises a pipeline stage array in which plural pipeline stages are connected in series, each pipeline stage performing a pipeline operation on an inputted analog voltage to output a digital voltage; a number-of-bits control circuit for outputting a number-of-bits selection signal which indicates whether the operation of each pipeline stage should be carried out or halted, according to a number-of-bits control signal which indicates a resolution; and a correction circuit for compensating a digital value to be output, according to the number-of-bits control signal. Therefore, when resolution of the A/D converter which is requested by the system is changed, only the pipeline stages required for realizing the requested resolution are operated while the other pipeline stages are halted, whereby a reduction in power consumption of the A/D converter is realized and, simultaneously, resolution of a digital value to be output can be compensated by the correction circuit, resulting in an A/D converter that never causes a breakdown of an output from the A/D converter.
According to a second aspect of the present invention, in the A/D converter according to the first aspect, the correction circuit comprises a correction A/D converter for receiving inputs of all of the pipeline stages, comparing an input that is selected from the inputs according to the number-of-bits selection signal, with a reference voltage value, and outputting a result of comparison as a partial digital value for correction which comprises at least one binary code; and a correction code conversion circuit for receiving the partial digital values which are outputted from all of the pipeline stages in the pipeline stage array, and the partial digital value for correction which is outputted from the correction A/D converter, and outputting at least one binary code according to the number-of-bits selection signal. Therefore, when resolution of a digital output signal which is requested by the system changes over a range of 1-N bits, a series of pipeline operations performed at the pipeline stages whose operations are not needed can be halted, without causing a breakdown of data output.
According to a third aspect of the present invention, in the A/D converter according to the first aspect, the correction circuit comprises a selection means for selecting an analog voltage value to be processed in a final pipeline stage, from among analog voltage values which are outputted from the plural pipeline stages except the final pipeline stage, according to the number-of-bits selection signal; and a correction code conversion circuit for receiving the partial digital value outputted from the final pipeline stage, and the partial digital values outputted from the respective pipeline stages in the pipeline stage array other than the final pipeline stage, and outputting corrected binary codes according to the number-of-bits selection signal. Therefore, when resolution of a digital output signal which is requested by the system changes over a range of 2-N bits, a series of pipeline operations performed at the pipeline stages whose operations are not needed can be halted, without causing a breakdown of data output.
According to a fourth aspect of the present invention, in the A/D converter according to the first aspect, the correction circuit comprises an offset control means for determining as to whether offset addition should be performed or not in the plural pipeline stages except the final pipeline stage, according to the number-of-bits control signal, and controlling the plural pipeline stages so as to output corrected binary codes. Therefore, when resolution of a digital output signal which is requested by the system changes over a range of 1-Nxe2x88x922 bits, or to N bits, a series of pipeline operations performed at the pipeline stages whose operations are not needed can be halted, without causing a breakdown of data output.